Fabrication method of semiconductor integrated circuit device

ABSTRACT

Upon formation of an impurity-added silicon film by a low-pressure CVD apparatus, diffusion of an impurity from another similar silicon film, which has already been formed over the inside walls of the deposition chamber, is suppressed in the following manner. After insertion of a semiconductor substrate, having a gate oxide film (insulating film) formed thereover, into the deposition chamber of a CVD apparatus (first film forming apparatus), the inside of the deposition chamber is heated while minimizing, relative to a time A required for heating of the inside of the deposition chamber under atmospheric pressure, a time B required for the subsequent heating in the deposition chamber under a pressure adjusted to vacuum or not greater than atmospheric pressure. The formation of an impurity-added silicon film is then started. At this time, the relation between A and B is controlled to satisfy the following equation: 0.1×B≦A≦13×B.

TECHNICAL FIELD

The present invention relates to a technique for the fabrication of asemiconductor integrated circuit device, and, more particularly, to atechnique that is effective when applied to a step of depositing, by CVD(Chemical Vapor Deposition), a silicon film having an impurity ionintroduced therein.

BACKGROUND OF THE INVENTION

As a material for a gate electrode of a MISFET (Metal InsulatorSemiconductor Field Effect Transistor), a polycrystalline silicon filmhaving an impurity added thereto is employed, for example. As theimpurity to be added, AsH₃, PH₃ or the like can be used for an n-channelMISFET, while B₂H₆ or the like can be used for a p-channel MISFET.

Such a polycrystalline silicon film can be formed, for example, by usinga low-pressure CVD apparatus. There is a description of a low-pressureCVD apparatus on p 187, “Technological Dictionary of SemiconductorEquipment (Fourth Edition)”, ed. by Semiconductor Equipment AssociationJapan, published by THE NIKKAN KOGYO SHIMBUN, LTD. on Nov. 20, 1997.

However, the present inventors have found that the use of such alow-pressure CVD apparatus involves problems, as described below.

A polycrystalline silicon film having an impurity added thereto, asdescribed above, is formed as a material for a gate electrode of aMISFET using a low-pressure CVD apparatus by inserting a semiconductorwafer into a deposition chamber, waiting for a predetermined time untilthe temperature in the deposition chamber becomes adequate, whilereducing the pressure in the deposition chamber to a vacuum or notgreater than atmospheric pressure, and then introducing a film forminggas in the deposition chamber. At this time, the polycrystalline siliconfilm is formed not only over the surface of the semiconductor wafer, butalso over the inside walls of the deposition chamber. When the formationof a similar polycrystalline silicon film over a newly-fed semiconductorwafer follows, it is also necessary to wait for a predetermined timeuntil the temperature in the deposition chamber increases to an adequatelevel, while reducing the pressure in the deposition chamber to a vacuumor not greater than atmospheric pressure. During this period, some ofthe impurity inevitably diffuses from the polycrystalline silicon filmformed on the inside walls of the deposition chamber. This diffusedimpurity scatters to the newly-fed semiconductor wafer on which apolycrystalline silicon film has not yet been formed, and it isintroduced into the gate oxide film already formed over the surface ofthe previously-fed semiconductor wafer. This deteriorates the insulationproperties of the gate oxide film.

An object of the present invention is to provide a technique forpreventing, upon formation of an impurity-added polycrystalline film bya low pressure CVD apparatus, diffusion of an impurity into the insidewalls of the deposition chamber from a similar polycrystalline filmwhich has already been formed.

The above-described and the other objects and novel features of thepresent invention will be apparent from the description provided hereinand the accompanying drawings.

SUMMARY OF THE INVENTION

Typical aspects of the inventions disclosed in the present applicationwill be outlined briefly.

The present invention provides a method which comprises the steps of:inserting a semiconductor substrate in a deposition chamber of a firstfilm forming apparatus; heating the inside of the deposition chamber;and, after the heating step, forming a silicon film, to which aconductive impurity has been added, over the semiconductor substrate bya chemical film forming method, the heating step comprising:

(a) heating the inside of the deposition chamber while maintaining thepressure in the deposition chamber at atmospheric pressure; and

(b) after the step (a), heating the inside of the deposition chamberwhile reducing the pressure inside of the deposition chamber to a vacuumor not greater than atmospheric pressure; wherein the step (a) takesmore time than the step (b).

The present invention also provides a method which comprises the stepsof: forming an insulating film over a semiconductor substrate and theninserting the semiconductor substrate in a deposition chamber of a firstfilm forming apparatus; heating the semiconductor substrate whilemaintaining the pressure in the deposition chamber at atmosphericpressure; after heating the semiconductor substrate, reducing thepressure in the deposition chamber to a vacuum or not greater thanatmospheric pressure, while heating the semiconductor substrate; andforming a semiconductor film, to which a conductive impurity has beenadded, over the insulating film by a chemical film forming method,wherein in the step of heating the semiconductor substrate whilemaintaining the pressure in the deposition chamber at atmosphericpressure, the semiconductor substrate is heated to a first temperatureof the semiconductor substrate upon film formation of the semiconductorfilm or the semiconductor substrate is heated to bring its temperatureclose to the first temperature.

The present invention also provides a method which comprises the stepsof forming an insulating film over a semiconductor substrate; insertingthe semiconductor substrate into a deposition chamber of a first filmforming apparatus; heating the semiconductor substrate to a firsttemperature, while keeping the pressure in the deposition chamber at afirst pressure; reducing the pressure in the deposition chamber to notgreater than a second pressure, while heating the semiconductorsubstrate; and forming a silicon film added a conductive impurity hasbeen added, over the insulating film of the semiconductor substrateheated to the first temperature by a chemical film forming method whilemaintaining the pressure in the deposition chamber at a vacuum or athird pressure not greater than atmospheric pressure; wherein the secondpressure is adjusted to be lower than the third pressure and the firstpressure is higher than the third pressure.

The present invention still further provides a method which comprisesthe steps of forming an insulating film over a semiconductor substrate;inserting the semiconductor substrate into a deposition chamber of afirst film forming apparatus; heating the semiconductor substrate whilekeeping the pressure in the deposition chamber at a first pressure;reducing the pressure in the deposition chamber to not greater than asecond pressure, while heating the semiconductor substrate; and forminga silicon film, to which a conductive impurity has been added, over theinsulating film by chemical film formation means, while keeping thepressure in the deposition chamber at a vacuum or a third pressure notgreater than atmospheric pressure; wherein the second pressure isadjusted to be lower than the third pressure, and in the silicon filmforming step, the semiconductor substrate is heated to bring itstemperature close to the first temperature, while maintaining the firstpressure at a level higher than the third pressure.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a fragmentary cross-sectional view illustrating a step in thefabrication of a semiconductor integrated circuit device according toone embodiment of the present invention;

FIG. 2 is a fragmentary cross-sectional view illustrating thesemiconductor integrated circuit device during a fabrication stepfollowing that of FIG. 1;

FIG. 3 is a diagram illustrating the composition of a CVD apparatus tobe used for the fabrication of the semiconductor integrated circuitdevice according to the one embodiment of the present invention;

FIG. 4 is a time chart upon deposition of a polycrystalline silicon filmduring fabrication of the semiconductor integrated circuit deviceaccording to the one embodiment of the present invention;

FIGS. 5( a) and 5(b) are graphs with accompanying diagrams illustratinginsulation properties of a gate oxide film when a polycrystallinesilicon film is formed by fabrication of the semiconductor integratedcircuit device according to the one embodiment of the present invention;

FIG. 6 is a time chart upon deposition of a polycrystalline silicon filmby another fabrication process used for comparison with that of thesemiconductor integrated circuit device according to the one embodimentof the present invention;

FIGS. 7( a) and 7(b) are graphs with accompanying diagrams illustratingthe insulation properties of a gate oxide film when a polycrystallinesilicon film is formed by a fabrication process different from that ofthe semiconductor integrated circuit device according to the oneembodiment of the present invention;

FIG. 8 is a fragmentary cross-sectional view of the semiconductorintegrated circuit device during a fabrication step following that ofFIG. 2;

FIG. 9 is a fragmentary cross-sectional view of the semiconductorintegrated circuit device during a fabrication step following that ofFIG. 8;

FIG. 10 is a time chart upon deposition of a polycrystalline siliconfilm during the fabrication of a semiconductor integrated circuit deviceaccording to another embodiment of the present invention;

FIG. 11 is a fragmentary cross-sectional view illustrating a step in thefabrication of a semiconductor integrated circuit device according to afurther embodiment of the present invention;

FIG. 12 is a fragmentary cross-sectional view of the semiconductorintegrated circuit device during a fabrication step following that ofFIG. 11;

FIG. 13 is a diagram showing the constitution of a CVD apparatus to beused for the fabrication of a semiconductor integrated circuit deviceaccording to a still further embodiment of the present invention;

FIG. 14 is a diagram illustrating a wafer holder of the CVD apparatus asillustrated in FIG. 13 and the constitution of semiconductor substratesdisposed over the wafer holder;

FIG. 15 is a time chart illustrating a pressure change in a depositionchamber upon deposition of a polycrystalline silicon film during thefabrication of the semiconductor integrated circuit device according toa still further embodiment of the present invention; and

FIG. 16 is a time chart illustrating a temperature change in adeposition chamber upon deposition of a polycrystalline silicon filmduring the fabrication of the semiconductor integrated circuit deviceaccording to a still further embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

The embodiments of the present invention will be described hereinafterwith reference to the accompanying drawings (in all of the drawings,elements having a like function will be identified by like referencenumerals and overlapping descriptions thereof will be omitted).

Embodiment 1

The method of fabrication of the semiconductor integrated circuit deviceaccording to this Embodiment 1 will be described in the order of FIGS. 1to 9.

As illustrated in FIG. 1, a semiconductor substrate 1 made of singlecrystal silicon is heat treated to form a silicon oxide film (pad oxidefilm) as thin as about 10 nm over the main surface of the substrate.Then, after deposition of a silicon nitride film to about 120 nm thickover the silicon oxide film by CVD, dry etching is conducted, using witha photoresist film as a mask, to remove the silicon nitride film andsilicon oxide film from an element isolation region.

By dry etching using the silicon nitride film as a mask, a groove whichis about 350 nm deep is formed in the semiconductor substrate 1 in theelement isolation region. The semiconductor substrate 1 is then heattreated to form a silicon oxide film as thin as about 10 nm over theinside walls of the groove in order to remove a damaged layer, that hasformed over the inside walls of the groove, by etching.

After deposition of a silicon oxide film 2 over the semiconductorsubstrate 1 by CVD, the semiconductor substrate 1 is heat treated todensify the silicon oxide film 2 so as to improve the quality of thesilicon oxide film 2. With the silicon nitride film serving as astopper, the silicon oxide film 2 is then polished by chemicalmechanical polishing (CMP) to leave it inside of the groove, whereby anelement isolating groove 3 having a planarized surface is formed.

The silicon nitride film remaining over the active region of thesemiconductor substrate 1 is then removed by wet etching with hotphosphoric acid, followed by implantation of an impurity ion (forexample, B (boron)) having a p type conductivity into the active regionto form a p well 4. The semiconductor substrate 1 is then heat treatedto form a clean gate oxide film (insulating film) 5 over the surface ofthe p well 4.

As illustrated in FIG. 2, a polycrystalline silicon film 6, to which animpurity has been added, having an n type conductivity, for example, PH₃is deposited by CVD (chemical film forming method). The deposition ofthis polycrystalline silicon film 6 can be conducted using, for example,a batch system low pressure CVD apparatus (first film formingapparatus), as illustrated in FIG. 3. This low pressure CVD apparatushas, in a deposition chamber DC thereof, a wafer holder WH for holdingthereon the semiconductor substrate 1. Into the deposition chamber DC,an SiH₄ gas is fed through a tube TU 1. The polycrystalline silicon film6 can be formed by the thermal decomposition of this SiH₄ gas. Byfeeding a PH₃ gas into the deposition chamber DC from tubes TU2 and TU3,PH₃ can be added to the polycrystalline silicon film 6. The SiH₄ gas andPH₃ gas introduced into the deposition chamber DC can be discharged froman exhaust port EX. The symbols in the drawing, that is, UU, U, CU, CL,L and LL, each indicate an index of a height at which the semiconductorsubstrate 1 is held in the deposition chamber DC.

In this Embodiment 1, the polycrystalline silicon film 6 is formed inaccordance with the time chart shown in FIG. 4. In FIG. 4, the symbol“T” stands for a time necessary for heating the inside of the depositionchamber DC before starting of the film formation, and it can be definedby the capacity in the deposition chamber. The symbol “A” stands for atime necessary for heating the inside of the deposition chamber underatmospheric pressure after the semiconductor substrate 1 is insertedinto the deposition chamber DC, while the symbol “B” stands for a timenecessary for the heating step when the pressure inside of thedeposition chamber DC is reduced to a vacuum or not greater thanatmospheric pressure. The time T is defined by the sum of A and B.

The polycrystalline silicon film 6 is inevitably formed not only overthe semiconductor substrate 1, but also over the inside walls of thedeposition chamber DC, and over the tubes TU1, TU2 and TU3 in thedeposition chamber DC as illustrated in FIG. 3. This CVD apparatus isused in repetition for the formation of the polycrystalline silicon film6. When a new semiconductor substrate 1 is inserted into the depositionchamber DC, the polycrystalline silicon film 6 has already been formedover various places in the deposition chamber DC. When the depositionchamber DC is heated for long hours under such a state, while thepressure in the deposition chamber DC is maintained at a vacuum or notgreater than the atmospheric pressure, PH₃ contained in thepolycrystalline silicon film 6, which has been formed over variousplaces in the deposition chamber DC, is diffused from thepolycrystalline silicon film 6. The resulting PH₃ is then introducedinto the gate oxide film 5 formed over the semiconductor substrate 1,and it presumably deteriorates the insulation properties of the gateoxide film 5.

The test made by the present inventors has revealed that diffusion ofPH₃ contained in the polycrystalline silicon film 6 formed over variousplaces in the deposition chamber DC can be suppressed by carrying outthe heating step under conditions satisfying the following equation:0.1×B≦A≦13×B. The present inventors carried out another test using a CVDapparatus equipped with a deposition chamber DC having a capacity ofabout 56 liters, specifying A and B to satisfy the above-describedconditions, that is, about 45 minutes and about 15 minutes,respectively, and dividing the main surface of the semiconductorsubstrate 1 into 296 regions. In this test, the deterioration of theinsulation properties of the gate insulating film 5 was studied in eachdivided region. In short, a voltage Vg is applied to the gate insulatingfilm 5 of each region thus divided, and a current Ig that is caused toflow therethrough is measured. The time T is defined as about 60 minuteswhen the deposition chamber DC has a capacity of about 56 liters. As aresult, when the semiconductor substrate 1 is held at a height of UU(refer to FIG. 3), a deterioration in the insulation properties wasdetected in only 3 regions among the 296 regions, as illustrated in FIG.5( a). When the semiconductor substrate 1 is held at a height of CL(refer to FIG. 3), a deterioration in the insulation properties wasdetected in only 8 regions among the 296 regions as illustrated in FIG.5( b). In FIGS. 5( a) and 5(b), the symbol “A” or “D” indicates a regionfrom which a deterioration in insulation properties was detected, whilethe symbol “/” indicates a region from which no deterioration ininsulation properties was detected. In other words, by heating thedeposition chamber DC while minimizing the time B necessary for heatingthe inside of the deposition chamber DC under a vacuum or not greaterthan atmospheric pressure, relative to the time A necessary for heatingin the deposition chamber DC under atmospheric pressure and then formingthe polycrystalline silicon film 6, a deterioration in the insulationproperties of the gate oxide film 5 can be prevented effectively withoutbeing influenced by the height at which the semiconductor substrate 1 isheld in the deposition chamber DC.

On the other hand, when the heating step in the deposition chamber DCunder atmospheric pressure is omitted, that is, when T=B, PH₃ isdiffused from the polycrystalline silicon film 6 that is formed overvarious places in the deposition chamber DC as soon as the heating stepdefined by B is started. The PH₃ is therefore introduced into the gateoxide film 5 formed over the semiconductor substrate 1, and itdeteriorates the insulation properties of the gate oxide film 5. Undersuch conditions, the present inventors made a similar test to thatdescribed with reference to FIGS. 5( a) and 5(b). As a result, when thesemiconductor substrate 1 is held at a height of UU (refer to FIG. 3), adeterioration in insulation properties was detected in 162 regions amongthe 296 regions, as illustrated in FIG. 7( a). When the semiconductorsubstrate 1 is held at a height of CL (refer to FIG. 3), a deteriorationin the insulation properties was detected in 140 regions among the 296regions, as illustrated in FIG. 7( b). In FIGS. 7( a) and 7(b), “A”, “C”and “D” each indicate a region in which a deterioration in insulationproperties was detected, while “/” indicates a region in which nodeterioration in insulation properties was detected. In consideration ofthe test results in combination with those shown in FIGS. 5( a) and5(b), it can be confirmed that diffusion of PH₃ from the polycrystallinesilicon film 6 formed over various places in the deposition chamber DCcan be prevented effectively by heating the inside of the depositionchamber DC under atmospheric pressure after insertion of thesemiconductor substrate 1 into the deposition chamber DC. This makes itpossible to effectively prevent a deterioration in the insulationproperties of the gate oxide film 5.

As illustrated in FIG. 8, using a photoresist film (not illustrated)patterned by photolithography as a mask, the polycrystalline siliconfilm 6 is dry etched to form a gate electrode 6N.

After removal of the photoresist film, a silicon oxide film is depositedover the semiconductor substrate 1 by CVD. Anisotropic etching of thesilicon oxide film is conducted by reactive ion etching (RIE), wherebyside wall spacers 7 are formed over the side walls of the gate electrode6N. An impurity (such as P) having an n type conductivity is implantedto form, in the p wells 4 on both sides of the gate electrode 6N, n typesemiconductor regions 8 constituting the source and drain regions of ann channel MISFET. Alternatively, it is possible to form lightly doped ntype semiconductor regions prior to the formation of the side wallspacers 7, and heavily doped n type semiconductor regions after theformation of the side wall spacers 7. By the steps so far described, ann channel MISFETQn can be fabricated.

After washing the surface of the semiconductor substrate 1, a Co(cobalt) film (not illustrated) is deposited over the semiconductorsubstrate 1, for example, by sputtering. The semiconductor substrate 1is then heat treated at about 600° C. to cause a silicidation reactionon the interface between the Co film and each of the n typesemiconductor regions 8 and gate electrode 6N to form a CoSi₂ layer 10.Since this CoSi₂ layer 10 is formed, it is possible to prevent theoccurrence of an alloy spike which will otherwise be formed between thesemiconductor substrate 1 and an interconnect formed over the n typesemiconductor regions 8 in a step to be described later.

After removal of the unreacted Co film by etching, heat treatment isconducted at about 700° C. to 800° C. to lower the resistance of theCoSi₂ layer 10. This makes it possible to reduce the contact resistancebetween the interconnect and the n type semiconductor regions 8.

As illustrated in FIG. 9, an interlayer insulating film 11 is formedover the n channel type MISFETQn, followed by dry etching of theinterlayer insulating film 11 using a photoresist film as a mask to forma through-hole 12 over the n type semiconductor regions 8. Then, aninterconnect 14 is formed over the interlayer insulating film 11,whereby the semiconductor integrated circuit device of this Embodiment 1is fabricated. The interlayer insulating film 11 is formed, for example,by depositing a silicon oxide film by CVD. The interconnect 14 isformed, for example, by depositing a metal film, such as a W or Alalloy, over the interlayer insulating film 11 by sputtering and thenpatterning the metal film by dry etching using a photoresist film as amask.

Multilayer interconnects may be formed by repeating the steps of formingthe interlayer insulating film 11, through-hole 12 and interconnect 14plural times.

Embodiment 2

In the method of fabrication of a semiconductor integrated circuitdevice according to this Embodiment 2, the polycrystalline silicon film6 (refer to FIG. 2) is formed in accordance with a time chart that isdifferent from that described with reference to FIG. 4 in connectionwith Embodiment 1.

The semiconductor integrated circuit device according to Embodiment 2 isfabricated in a similar manner to that of Embodiment 1 through the stepsdescribed with reference to FIG. 1. Then, the semiconductor substrate 1is inserted into the deposition chamber DC of the CVD apparatus asillustrated in FIG. 3. In accordance with the time chart of FIG. 10, apolycrystalline silicon film 6 is formed. In this Embodiment 2, thepressure in the deposition chamber DC is reduced to a vacuum or notgreater than atmospheric pressure immediately after the insertion of thesemiconductor substrate 1 into the deposition chamber DC, and heattreatment in the deposition chamber DC is conducted. The time Tnecessary for heating the inside of the deposition chamber DC beforestarting the formation of the polycrystalline silicon film 6 is similarto that of Embodiment 1, but during this heating step, as defined by thesymbol T, deposition of a thin non-doped polycrystalline silicon film 6is carried out. With this non-doped polycrystalline silicon film 6, thegate oxide film 5 is covered so that even if heating inside of thedeposition chamber DC, while reducing the pressure in the depositionchamber DC to a vacuum or not greater than atmospheric pressure, causesdiffusion of PH₃ from the polycrystalline silicon film 6, which hasalready been formed over various places in the deposition chamber DC,the non-doped polycrystalline silicon film 6 protects the gate oxidefilm 5 and can prevent introduction of PH₃ into the gate oxide film 5.In this Embodiment 2, by the heating step as defined by the time T afterthe formation of such a non-doped polycrystalline silicon film 6, theintended polycrystalline silicon film 6 with PH₃ added thereto isdeposited.

Then, by employing similar steps to those described with reference toFIGS. 8 and 9 in connection with Embodiment 1, the semiconductorintegrated circuit device according to Embodiment 2 is fabricated.

Embodiment 3

The method of fabrication of a semiconductor integrated circuit deviceaccording to this Embodiment 3 will be described next with reference toFIGS. 11 and 12.

The fabrication of the semiconductor integrated circuit device accordingto Embodiment 3 is similar to that of Embodiment 1 through the steps asdescribed with reference to FIG. 1. Then, as illustrated in FIG. 11, athin intrinsic polycrystalline silicon film 6A is deposited over thesemiconductor substrate 1 by using a film forming apparatus (second filmforming apparatus) that is different from the CVD apparatus as describedwith reference to FIG. 3 in connection with Embodiment 1. By thisdeposition, the gate oxide film 5 is covered with the intrinsicpolycrystalline silicon film 6A. Moe specifically, even if PH₃ isdiffused from the polycrystalline silicon film 6, which has already beenformed over various places in the deposition chamber DC, upon subsequentdeposition of a new polycrystalline silicon film 6, to which PH₃ isadded, by the CVD apparatus as described with reference to FIG. 3 inconnection with Embodiment 1, the intrinsic polycrystalline silicon film6 protects the gate oxide film 5 and prevents the PH₃ from beingintroduced into the gate oxide film 5. As a result, a deterioration inthe insulation properties of the gate oxide film 5 can be prevented.

As illustrated in FIG. 12, another polycrystalline silicon film 6 isdeposited by CVD over the intrinsic polycrystalline silicon film 6,followed by steps similar to those described with reference to FIGS. 8and 9 in connection with Embodiment 1, whereby the semiconductorintegrated circuit device of this Embodiment 3 is fabricated.

Embodiment 4

In this Embodiment 4, a more specific supplementary explanation relativeto the Embodiment 1 will be given.

FIG. 13 illustrates more details of the constitution of the low pressureCVD apparatus described with reference to FIG. 3 in connection withEmbodiment 1.

As illustrated in FIG. 13, a wafer holder can be moved verticallybetween the deposition chamber DC and a transfer chamber TA, which isdisposed below the deposition chamber DC. After a predetermined numberof semiconductor substrates 1 have been placed on the wafer holder WH inthe transfer chamber TA, the wafer holder WH is lifted into thedeposition chamber DC. After completion of the formation of apolycrystalline silicon film 6 (semiconductor film (refer to FIG. 2))over the semiconductor substrate 1, the wafer holder WH is moved down tothe transfer chamber TA again. Thus, the low pressure CVD apparatus ofthis Embodiment has a vertical deposition chamber DC.

In the transfer chamber TA, a cassette shelf CT is formed for disposingwafer cassettes therein. In a wafer cassette CA, a plurality of thesemiconductor substrates 1 can be stored. In this Embodiment, thetemperature inside of the transfer chamber TA is room temperature (about20° C.).

In the transfer chamber TA, disposal of the semiconductor substrate 1 onthe wafer holder WH and ejection, from the wafer holder WH, of thesemiconductor substrate 1 over which the polycrystalline silicon film 6has been formed are carried out by a carrier robot. This carrier robothas a plurality of carrier arms ARM for carrying the semiconductorsubstrate 1 while causing the backside thereof to adsorb to the arms. Byvertical, horizontal and rotary movements, it takes out a plurality ofthe semiconductor substrates 1 simultaneously from the wafer cassette CAand disposes these semiconductor substrates 1 on the wafer holder WH.When a predetermined number of the semiconductor substrates 1 (about 150substrates when the diameter of the semiconductor substrate 1 is about150 mm (about 6 inch)) are placed on the wafer holder WH, the waferholder WH is moved up to the deposition chamber DC, and thepolycrystalline silicon film 6 is formed over each semiconductorsubstrate 1. When the formation of the polycrystalline silicon film 6has finished, the wafer holder WH is moved down to the transfer chamberTA, and the carrier robot CR takes out the semiconductor substrate 1from the wafer holder WH and stores it in the wafer cassette CA.

The deposition chamber DC has, outside thereof, heaters H1, H2, H3 andH4 for heating the deposition chamber DC. Heating by these heaters H1,H2, H3 and H4 makes it possible to constantly keep the temperatureinside of the deposition chamber DC at from 500 to 600° C.

These heaters H1, H2, H3 and H4 can be set at respective temperatures,and a temperature gradient can be formed for the heating of thedeposition chamber DC. When the film forming gases, that is, SiH₄ andPH₃ gases, are introduced from the lower part of the deposition chamberDC, the temperatures of the heaters are set so that the heatingtemperatures become higher progressively from the heater H4 that isinstalled at the relatively lower part of the deposition chamber towardthe heater 1 installed at the relatively upper part of the depositionchamber DC. The film forming gases introduced from the lower part of thedeposition chamber DC go up while being thermally decomposed. The filmforming gases therefore experience a slow down in the pace of thermaldecomposition as they go up toward the upper part of the depositionchamber DC. In other words, it becomes difficult to deposit thepolycrystalline silicon film 6 over the semiconductor substrate 1. Asdescribed above, by forming a temperature gradient so that the heatingtemperature becomes progressively higher from the heater 4 toward theheater 1, thermal decomposition of the film forming gases can bepromoted even at the upper part of the deposition chamber DC. Since itis possible to set the temperatures of the heaters H1, H2, H3 and H4independently, the deposition chamber can, of course, be heated byheaters that are set at almost the same temperature.

In this Embodiment 4, four heaters H1, H2, H3 and H4 are installedoutside of the deposition chamber DC. It is also possible to use oneheater or plural heaters other than four insofar as similar heating tothat provided by the four heaters H1, H2, H3 and H4 can be attained.Plural heaters that are different in size can also be installed.

FIG. 14 is a diagram illustrating a method of disposing thesemiconductor substrate 1 on the wafer holder WH. In FIG. 14,illustration of the semiconductor substrate 1 (which will be a product)over which the semiconductor integrated circuit device of thisEmbodiment is to be formed in practice is omitted.

In this Embodiment, about 150 semiconductor substrates 1 having adiameter of about 150 mm (6 inches) are disposed in the wafer holder WH.Of these, the 20 substrates disposed at the bottom part and the 5substrates disposed at the top part of the wafer holder WH are dummywafers DW for rectifying the film forming gases in the depositionchamber DC during film formation. Between the upper and bottom dummywafers DW, several monitor wafers MW (for example, 5 wafers) aredisposed at proper distances. These monitor wafers MW are inserted inorder to measure the concentration of PH₃ doped into the polycrystallinesilicon film 6 and to measure the thickness of the depositedpolycrystalline silicon film 6. These dummy wafers DW and monitor wafersMW are prepared separately from the semiconductor substrates 1 overwhich the semiconductor integrated circuit device of this Embodiment isto be formed in practice.

FIG. 15 illustrates, of the time charts illustrated in FIGS. 4 and 6 inconnection with Embodiment 1, a pressure change in the depositionchamber DC until the formation of the polycrystalline silicon film 6 isstarted. FIG. 16 illustrates a temperature change of the semiconductorsubstrate 1 with the passage of time until the formation of thepolycrystalline silicon film 6 is started. The pressure changeillustrated in FIG. 15 and the temperature change illustrated in FIG. 16each starts when the insertion of the wafer holder WH into thedeposition chamber DC is completed. In the time chart illustrated inFIG. 6 for Embodiment 1, a pressure reduction in the deposition chamberDC is started as soon as the insertion of the wafer holder WH into thedeposition chamber DC is completed. In spite of the intention to start apressure reduction as soon as the insertion of the wafer holder WH intothe deposition chamber DC is completed, a pressure reduction in mostcases starts after some time lag (for example, several seconds) inactual practice. FIG. 15 illustrates a pressure change in considerationof such a time lag. In this Embodiment, the heaters H1, H2, H3 and H4used for heating of the deposition chamber DC are all set at a similartemperature and a temperature gradient is not formed for the heating ofthe deposition chamber DC.

FIG. 15 shows the time spent for heating of the deposition chamber DCuntil the pressure reduction in the deposition chamber is started. Inthis diagram, the symbol A indicates the time of the time chart(corresponding to FIG. 4 in connection with Embodiment 1) in the filmforming unit of this Embodiment, while the symbol Al indicates the timeof the time chart (corresponding to FIG. 6 in connection withEmbodiment 1) in the film forming means employed for comparison withthat of this Embodiment.

The temperature of the semiconductor substrate 1 shown in FIG. 16 isthat of the semiconductor substrate 1 (first semiconductor substrate)disposed at the lowest part of the wafer holder WH among thesemiconductor substrates 1 disposed therein. Since, upon insertion ofthe wafer holder WH into the deposition chamber DC, the insertion of theupper part of the wafer holder WH starts first and the temperatureinside of the deposition chamber DC is heated constantly from about 500°C. to 600° C., the semiconductor substrate 1 which is disposed at arelatively upper part is heated during the insertion of the wafer holderWH into the deposition chamber DC. When the insertion of the waferholder WH into the deposition chamber DC is completed, there exists, forexample, a temperature difference such that the semiconductor substrate1 at the top part and the semiconductor substrate 1 at the lowest part,for example, are about 300° C. and about 200° C., respectively. Evenwhen the semiconductor substrate 1 at the top part reaches a temperaturepermitting film formation by heating through the heaters H1, H2, H3 andH4, the semiconductor substrate 1 at the lowest part does not alwaysreach a temperature permitting film formation. In other words, it ispossible to judge whether all the semiconductor substrates 1 disposed inthe wafer holder WH have reached the temperature permitting filmformation or not, by confirming that the semiconductor substrate 1 atthe lowest part reaches the temperature permitting film formation. Whena temperature gradient is formed for the heating by the heaters H1, H2,H3 and H4 and, thereby, a semiconductor substrate 1 other than thesemiconductor substrate 1 at the lowest part reaches the temperaturepermitting film formation last, it is only necessary to observe atemperature change in a semiconductor substrate 1 other than thesemiconductor substrate 1 at the lowest part.

As illustrated in FIG. 15, in the film forming means according to thisEmbodiment, a pressure reduction in the deposition chamber DC is startedafter the insertion of the semiconductor substrate 1 into the depositionchamber DC is completed, and the semiconductor substrate 1 is heated toat least about 90% of the temperature (first temperature (for example,about 500° C.)) at which the film formation can be started. In thisEmbodiment, “at least about 90% of the temperature” is based on thedegrees Celsius. As described above, the temperature in the depositionchamber DC is constantly heated to about 500 to 600° C. This means thatthe semiconductor substrate 1 can be maintained at a temperaturepermitting film formation so that when the temperature reaches atemperature permitting film formation, the temperature change of thesemiconductor substrate 1 stops and becomes stable. Until the pressurereduction is started, the pressure in the deposition chamber DC is keptat atmospheric pressure (first pressure). In other words, the depositionchamber DC is kept at a pressure (first pressure) at least equal to thepressure (third pressure) under which the film formation is conducted.

The time until the pressure reduction in the deposition chamber DC isstarted after the insertion of the wafer holder WH into the depositionchamber DC is designated as “A”. The pressure reduction in thedeposition chamber DC stops when the pressure in the deposition chamberDC becomes that permitting film formation and the deposition chamber DCis maintained at this pressure. In other words, after the pressure ofthe deposition chamber DC is reduced to a pressure (second pressure) notgreater than a pressure (third pressure) under which the film formationis conducted, a film forming gas for forming a film in the depositionchamber DC is fed and film formation is conducted under the pressure forfilm formation.

In the case of the film forming means compared with that of thisEmbodiment, although some interval time Al exists until the starting ofthe pressure reduction in the deposition chamber DC after the waferholder WH is inserted into the deposition chamber DC, the pressurereduction in the deposition chamber DC is started almost just after theinsertion of the wafer holder WH into the deposition chamber DC. Inother words, the pressure reduction in the deposition chamber DC isconducted before the temperature of the semiconductor substrate 1reaches a temperature permitting film formation. The semiconductorsubstrate 1 is therefore heated in the deposition chamber DC under apressure close to vacuum compared with that in the film forming means ofthis Embodiment. This makes it difficult to increase the temperature ofthe semiconductor substrate 1 compared with that in the film formingmeans of this Embodiment (refer to FIG. 16). As in the film formingmeans of this Embodiment, the pressure reduction in the depositionchamber DC stops when the pressure in the deposition chamber DC becomesa pressure permitting film formation, and, under this pressure, theinside of the deposition chamber DC is maintained.

Both in the film forming means of this Embodiment and the film formingmeans compared therewith, the pressure reduction in the depositionchamber DC is carried out within a time short enough not to generateforeign matter in the deposition chamber DC. This is because whenanother treatment is conducted during pressure reduction, there is adanger of foreign matter being introduced in the deposition chamber DC;and, when the foreign matter is introduced in the deposition chamber DC,there is a fear that there will be a deterioration in the quality of thepolycrystalline silicon film thus formed.

The present invention has been described based on various embodiments ofthe present invention. However, should be borne in mind that the presentinvention is not limited to the described embodiments. It is needless tosay that modifications can be made within an extent not departing fromthe scope of the invention.

For example, PH₃ was added to the polycrystalline silicon film in theabove-described embodiment, but AsH₃ may be added, instead.

In the above-described embodiment, an n-channel MISFET was formed, butthe fabrication of a semiconductor integrated circuit device accordingto the present invention can also be applied to the formation of a pchannel MISFET. In this case, B₂H₆ or the like is added to thepolycrystalline silicon film which will serve as a gate electrode.

The above-described method of formation of a polycrystalline siliconfilm can be applied not only to the formation of a polycrystallinesilicon film which is to serve as a gate electrode material, but also tothe formation of a polycrystalline silicon film which is to be used as alower electrode of the capacitor of a DRAM.

The present invention can be applied to the fabrication of asemiconductor integrated circuit device, including a MISFET and a DRAM(Dynamic Random Access Memory), and to the fabrication of amicromachine.

1. A fabrication method of a semiconductor integrated circuit device,comprising the steps of: (a) forming an insulating film over asemiconductor wafer; (b) after the step (a), inserting the semiconductorwafer into a thermal chemical vapor deposition chamber of a first filmforming apparatus; (c) heating the inside of the chamber; and (d) afterthe step (c), forming a silicon film added with a conductive impurityover the insulating film by a chemical vapor deposition method, saidstep (c) comprising the sub-steps of: (c1) heating the inside of thechamber while keeping the inside of the chamber at atmospheric pressure;and (c2) after the sub-step (c1), heating the inside of the chamberwhile adjusting the pressure inside of the chamber to vacuum or notgreater than atmospheric pressure, wherein a time required for thesub-step (c1) is longer than a time required for the sub-step (c2).
 2. Afabrication method of a semiconductor integrated circuit device,comprising the steps of: (a) forming an insulating film over asemiconductor wafer; (b) after the step (a), inserting the semiconductorwafer into a thermal chemical vapor deposition chamber of a first filmforming apparatus; (c) heating the inside of the chamber; and (d) afterthe step (c), forming a silicon film added with a conductive impurityover the insulating film by a chemical vapor deposition method, saidstep (c) comprising the sub-steps of: (c1) heating the inside of thechamber while keeping the inside of the chamber at atmospheric pressure;and (c2) after the sub-step (c1), heating the inside of the chamberwhile adjusting a pressure inside of the chamber to vacuum or notgreater than atmospheric pressure, wherein a time required for thesub-step (c1) is 0.1 time or greater but not greater than 13 times aslong as a time required for the sub-step (c2).
 3. A fabrication methodof a semiconductor integrated circuit device, comprising the steps of:(a) forming an insulating film over a semiconductor wafer; (b) after thestep (a), inserting the semiconductor wafer into a thermal chemicalvapor deposition chamber of a first film forming apparatus; (c) heatingthe semiconductor wafer while keeping the inside of the chamber at afirst pressure; (d) after the step (c), reducing a pressure in thechamber to be not greater than a second pressure, while heating thesemiconductor wafer; and (e) forming a silicon film added with aconductive impurity over the insulating film by a chemical vapordeposition method while keeping a pressure in the chamber at vacuum or athird pressure not greater than atmospheric pressure, wherein in thestep (d), pressure is reduced so that the second pressure becomes lowerthan the third pressure, wherein in the step (c), the semiconductorwafer is heated to bring a temperature thereof close to the firsttemperature while maintaining the first pressure to be higher than thethird pressure, and wherein a time required for the step (c) is longerthan that required for the step (d).
 4. A fabrication method of asemiconductor integrated circuit device, comprising the steps of: (a)forming an insulating film over a semiconductor wafer; (b) after thestep (a), inserting the semiconductor wafer into a thermal chemicalvapor deposition chamber of a first film forming apparatus; (c) heatingthe semiconductor wafer while keeping the inside of the chamber at afirst pressure; (d) after the step (c), reducing a pressure in thechamber to be not greater than a second pressure, while heating thesemiconductor wafer; and (e) forming a silicon film added with aconductive impurity over the insulating film by a chemical vapordeposition method while keeping a pressure in the chamber at vacuum or athird pressure not greater than atmospheric pressure, wherein in thestep (d), pressure is reduced so that the second pressure becomes lowerthan the third pressure, wherein in the step (c), the semiconductorwafer is heated to bring a temperature thereof close to the firsttemperature while maintaining the first pressure to be higher than thethird pressure, and wherein the time required for the step (c) is 0.1time or greater but not greater than 13 times as long as the timerequired for the step (d).